View MC74HC4046ADG_640947.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

MC74HC4046A Phase-Locked Loop
High-Performance Silicon-Gate CMOS
The MC74HC4046A is similar in function to the MC14046 Metal gate CMOS device. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LSTTL outputs. The HC4046A phase-locked loop contains three phase comparators, a voltage-controlled oscillator (VCO) and unity gain op-amp DEM OUT. The comparators have two common signal inputs, COMP IN, and SIG IN. Input SIG IN and COMP IN can be used directly coupled to large voltage signals, or indirectly coupled (with a series capacitor to small voltage signals). The self-bias circuit adjusts small voltage signals in the linear region of the amplifier. Phase comparator 1 (an exclusive OR gate) provides a digital error signal PC1 OUT and maintains 90 degrees phase shift at the center frequency between SIG IN and COMP IN signals (both at 50% duty cycle). Phase comparator 2 (with leading-edge sensing logic) provides digital error signals PC2 OUT and PCP OUT and maintains a 0 degree phase shift between SIG IN and COMP IN signals (duty cycle is immaterial). The linear VCO produces an output signal VCO OUT whose frequency is determined by the voltage of input VCO IN signal and the capacitor and resistors connected to pins C1A, C1B, R1 and R2. The unity gain op-amp output DEM OUT with an external resistor is used where the VCO IN signal is needed but no loading can be tolerated. The inhibit input, when high, disables the VCO and all op-amps to minimize standby power consumption. Applications include FM and FSK modulation and demodulation, frequency synthesis and multiplication, frequency discrimination, tone decoding, data synchronization and conditioning, voltage-to-frequency conversion and motor speed control.
Features
http://onsemi.com MARKING DIAGRAMS
16 16 1 PDIP-16 N SUFFIX CASE 648 1 16 16 1 SOIC-16 D SUFFIX CASE 751B 1 16 16 1 TSSOP-16 DT SUFFIX CASE 948F 1 16 16 1 SOEIAJ-16 F SUFFIX CASE 966 1 74HC4046A ALYWG HC40 46A ALYWG G HC4046AG AWLYWW MC74HC4046AN AWLYYWWG
* * * * * * * * * * *
Output Drive Capability: 10 LSTTL Loads Low Power Consumption Characteristic of CMOS Devices Operating Speeds Similar to LSTTL Wide Operating Voltage Range: 3.0 to 6.0 V Low Input Current: 1.0 mA Maximum (except SIGIN and COMPIN) In Compliance with the Requirements Defined by JEDEC Standard No. 7A Low Quiescent Current: 80 mA Maximum (VCO disabled) High Noise Immunity Characteristic of CMOS Devices Diode Protection on all Inputs Chip Complexity: 279 FETs or 70 Equivalent Gates Pb-Free Packages are Available*
A = Assembly Location L, WL = Wafer Lot Y, YY = Year W, WW = Work Week G = Pb-Free Package G = Pb-Free Package (Note: Microdot may be in either location)
ORDERING INFORMATION
See detailed ordering and shipping information in the package dimensions section on page 5 of this data sheet.
*For additional information on our Pb-Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.
(c) Semiconductor Components Industries, LLC, 2005
1
June, 2005 - Rev. 8
Publication Order Number: MC74HC4046A/D
MC74HC4046A
Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Symbol PCPOUT PC1OUT COMPIN VCOOUT INH C1A C1B GND VCOIN DEMOUT R1 R2 PC2OUT SIGIN PC3OUT VCC Name and Function Phase Comparator Pulse Output Phase Comparator 1 Output Comparator Input VCO Output Inhibit Input Capacitor C1 Connection A Capacitor C1 Connection B Ground (0 V) VSS VCO Input Demodulator Output Resistor R1 Connection Resistor R2 Connection Phase Comparator 2 Output Signal Input Phase Comparator 3 Output Positive Supply Voltage PCPout PC1out COMP in VCOout INH C1A C1B GND 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 VCC PC3out SIGin PC2out R2 R1 DEMout VCOin
Figure 1. Pin Assignment
II I II I IIIIIIIIIIIIIIIIIIIIIII II I III I IIIIIIIIIIIIIIIIIIIIIII II I I I I IIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIII I III II I IIIIIIIIIIIIIIIIIIIII I IIIIIIIIIIIIIIIIIIIIIII II I III IIIIIIIIIIIIIIIIIIIIIII II II I I IIIIIIIIIIIIIIIIIIIIIII II IIIIIIIIIIIIIIIIIIIIIII II I I IIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIII II I I IIIIIIIIIIIIIIIIIIIIIII II I I III II I IIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIII II II I I IIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIII II I I IIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIII II I I I IIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIII II IIIIIIIIIIIIIIIIIIIIIII
MAXIMUM RATINGS
Symbol VCC Vin Parameter Value Unit V V V DC Supply Voltage (Referenced to GND) DC Input Voltage (Referenced to GND) - 0.5 to + 7.0 - 1.5 to VCC + 1.5 - 0.5 to VCC + 0.5 20 25 50 750 500 Vout Iin DC Output Voltage (Referenced to GND) DC Input Current, per Pin mA mA mA Iout DC Output Current, per Pin ICC PD DC Supply Current, VCC and GND Pins Power Dissipation in Still Air Storage Temperature Plastic DIP SOIC Package mW _C _C Tstg TL - 65 to + 150 260 Lead Temperature, 1 mm from Case for 10 Seconds Plastic DIP and SOIC Package
This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance circuit. For proper operation, Vin and Vout should be constrained to the range GND v (Vin or Vout) v VCC. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or VCC). Unused outputs must be left open.
Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit values (not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied, damage may occur and reliability may be affected. Derating -- Plastic DIP: - 10 mW/_C from 65_ to 125_C SOIC Package: - 7 mW/_C from 65_ to 125_C For high frequency or heavy load considerations, see Chapter 2 of the ON Semiconductor High-Speed CMOS Data Book (DL129/D).
RECOMMENDED OPERATING CONDITIONS
II I I IIIIIIIIIIIIIIIIIIIIIII III I I III I I IIIIIIIIIIIIIIIIIIIIIII II I I II I I I IIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIII III III I I IIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIII II IIIIIIIIIIIIIIIIIIIIIII III I II I IIIIIIIIIIIIIIIIIIIIIII III III I I I I I IIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIII I
Symbol VCC Parameter Min 3.0 Max 6.0 Unit V DC Supply Voltage (Referenced to GND) VCC DC Supply Voltage (Referenced to GND) NON-VCO 2.0 0 6.0 V Vin, Vout TA DC Input Voltage, Output Voltage (Referenced to GND) Operating Temperature, All Package Types Input Rise and Fall Time (Pin 5) VCC V - 55 0 0 0 + 125 1000 500 400 _C ns tr, tf VCC = 2.0 V VCC = 4.5 V VCC = 6.0 V
http://onsemi.com
2
MC74HC4046A
[Phase Comparator Section] DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)
Guaranteed Limit Symbol VIH Parameter Minimum High-Level Input Voltage DC Coupled SIGIN, COMPIN Maximum Low-Level Input Voltage DC Coupled SIGIN, COMPIN Minimum High-Level Output Voltage PCPOUT, PCnOUT Test Conditions Vout = 0.1 V or VCC - 0.1 V |Iout| 20 mA Vout = 0.1 V or VCC - 0.1 V |Iout| 20 mA Vin = VIH or VIL |Iout| 20 mA Vin = VIH or VIL |Iout| 4.0 mA |Iout| 5.2 mA VOL Maximum Low-Level Output Voltage Qa-Qh PCPOUT, PCnOUT Vout = 0.1 V or VCC - 0.1 V |Iout| 20 mA Vin = VIH or VIL |Iout| 4.0 mA |Iout| 5.2 mA Iin Maximum Input Leakage Current SIGIN, COMPIN Vin = VCC or GND VCC V 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 4.5 6.0 2.0 4.5 6.0 4.5 6.0 2.0 3.0 4.5 6.0 6.0 - 55 to 25_C 1.5 3.15 4.2 0.5 1.35 1.8 1.9 4.4 5.9 3.98 5.48 0.1 0.1 0.1 0.26 0.26 3.0 7.0 18.0 30.0 0.5 85C 1.5 3.15 4.2 0.5 1.35 1.8 1.9 4.4 5.9 3.84 5.34 0.1 0.1 0.1 0.33 0.33 4.0 9.0 23.0 38.0 5.0 125C 1.5 3.15 4.2 0.5 1.35 1.8 1.9 4.4 5.9 3.7 5.2 0.1 0.1 0.1 0.4 0.4 5.0 11.0 27.0 45.0 10 mA V Unit V
VIL
V
VOH
V
IOZ
Maximum Three-State Leakage Current PC2OUT Maximum Quiescent Supply Current (per Package) (VCO disabled) Pins 3, 5 and 14 at VCC Pin 9 at GND; Input Leakage at Pins 3 and 14 to be excluded
Output in High-Impedance State Vin = VIH or VIL Vout = VCC or GND Vin = VCC or GND |Iout| = 0 mA
mA
ICC
6.0
4.0
40
160
mA
NOTE: Information on typical parametric values can be found in Chapter 2 of the ON Semiconductor High-Speed CMOS Data Book (DL129/D).
[Phase Comparator Section] AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, Input tr = tf = 6.0 ns)
Guaranteed Limit Symbol tPLH, tPHL tPLH, tPHL tPLH, tPHL tPLZ, tPHZ tPZH, tPZL tTLH, tTHL Parameter Maximum Propagation Delay, SIGIN/COMPIN to PC1OUT (Figure 2) Maximum Propagation Delay, SIGIN/COMPIN to PCPOUT (Figure 2) Maximum Propagation Delay, SIGIN/COMPIN to PC3OUT (Figure 2) Maximum Propagation Delay, SIGIN/COMPIN Output Disable Time to PC2OUT (Figures 3 and 4) Maximum Propagation Delay, SIGIN/COMPIN Output Enable Time to PC2OUT (Figures 3 and 4) Maximum Output Transition Time (Figure 2) VCC V 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 - 55 to 25_C 175 35 30 340 68 58 270 54 46 200 40 34 230 46 39 75 15 13 85C 220 44 37 425 85 72 340 68 58 250 50 43 290 58 49 95 19 16 125C 265 53 45 510 102 87 405 81 69 300 60 51 345 69 59 110 22 19 Unit ns
ns
ns
ns
ns
ns
http://onsemi.com
3
MC74HC4046A
[VCO Section] DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)
Guaranteed Limit Symbol VIH Parameter Minimum High-Level Input Voltage INH Maximum Low-Level Input Voltage INH Minimum High-Level Output Voltage VCOOUT Test Conditions Vout = 0.1 V or VCC - 0.1 V |Iout| 20 mA Vout = 0.1 V or VCC - 0.1 V |Iout| 20 mA Vin = VIH or VIL |Iout| 20 mA Vin = VIH or VIL |Iout| 4.0 mA |Iout| 5.2 mA VOL Maximum Low-Level Output Voltage VCOOUT Vout = 0.1 V or VCC - 0.1 V |Iout| 20 mA Vin = VIH or VIL |Iout| 4.0 mA |Iout| 5.2 mA Iin Maximum Input Leakage Current INH, VCOIN Vin = VCC or GND VCC V 3.0 4.5 6.0 3.0 4.5 6.0 3.0 4.5 6.0 4.5 6.0 3.0 4.5 6.0 4.5 6.0 6.0 Min VVCO IN Operating Voltage Range at VCOIN over the range specified for R1; For linearity see Fig. 15A, Parallel value of R1 and R2 should be > 2.7 kW R1 Resistor Range INH = VIL 3.0 4.5 6.0 0.1 0.1 0.1 - 55 to 25_C 2.1 3.15 4.2 0.90 1.35 1.8 1.9 4.4 5.9 3.98 5.48 0.1 0.1 0.1 0.26 0.26 0.1 Max 1.0 2.5 4.0 Min 0.1 0.1 0.1 85C 2.1 3.15 4.2 0.9 1.35 1.8 1.9 4.4 5.9 3.84 5.34 0.1 0.1 0.1 0.33 0.33 1.0 Max 1.0 2.5 4.0 Min 0.1 0.1 0.1 125C 2.1 3.15 4.2 0.9 1.35 1.8 1.9 4.4 5.9 3.7 5.2 0.1 0.1 0.1 0.4 0.4 1.0 Max 1.0 2.5 4.0 V mA V Unit V
VIL
V
VOH
V
3.0 4.5 6.0 3.0 4.5 6.0
3.0 3.0 3.0 3.0 3.0 3.0 40 40 40
300 300 300 300 300 300 No Limit
3.0 3.0 3.0 3.0 3.0 3.0
300 300 300 300 300 300
3.0 3.0 3.0 3.0 3.0 3.0
300 300 300 300 300 300
kW
R2
C1
Capacitor Range
3.0 4.5 6.0
pF
[VCO Section] AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, Input tr = tf = 6.0 ns)
Guaranteed Limit VCC V 3.0 4.5 6.0 3.0 4.5 6.0 3.0 4.5 6.0 3.0 4.5 6.0 3 11 13 See Figures 16A, B, C - 55 to 25_C Min Max 85C Min Max 125C Min Max Unit %/K
Symbol Df/T Frequency Stability with Temperature Changes (Figure 14A, B, C) VCO Center Frequency (Duty Factor = 50%) (Figure 15A, B, C, D) VCO Frequency Linearity
Parameter
fo
MHz
DfVCO
%
VCO
Duty Factor at VCOOUT
Typical 50%
%
http://onsemi.com
4
MC74HC4046A
[Demodulator Section] DC ELECTRICAL CHARACTERISTICS
Guaranteed Limit - 55 to 25_C Min 50 50 50 Max 300 300 300 See Figure 13 85C Min Max 125C Min Max Unit kW
Symbol RS
Parameter Resistor Range
Test Conditions At RS > 300 kW the Leakage Current can Influence VDEMOUT Vi = VVCOIN = 1/2 VCC; Values taken over RS Range. VDEMOUT = 1/2 VCC
VCC V 3.0 4.5 6.0 3.0 4.5 6.0 3.0 4.5 6.0
VOFF
Offset Voltage VCOIN to VDEMOUT Dynamic Output Resistance at DEMOUT
mV
RD
Typical 25 W
W
ORDERING INFORMATION
Device MC74HC4046AN MC74HC4046ANG MC74HC4046AD MC74HC4046ADG MC74HC4046ADR2 MC74HC4046ADR2G MC74HC4046ADT MC74HC4046ADTG MC74HC4046ADTR2 MC74HC4046ADTR2G MC74HC4046AF MC74HC4046AFG MC74HC4046AFEL MC74HC4046AFELG Package PDIP-16 PDIP-16 (Pb-Free) SOIC-16 SOIC-16 (Pb-Free) SOIC-16 SOIC-16 (Pb-Free) TSSOP-16* TSSOP-16* TSSOP-16* TSSOP-16* SOEIAJ-16 SOEIAJ-16 (Pb-Free) SOEIAJ-16 SOEIAJ-16 (Pb-Free) Shipping 2000 Units / Box 2000 Units / Box 48 Units / Rail 48 Units / Rail 2500 Units / Reel 2500 Units / Reel 96 Units / Rail 96 Units / Rail 2500 Units / Reel 2500 Units / Reel 50 Units / Rail 50 Units / Rail 2000 Units / Reel 2000 Units / Reel
For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. *This package is inherently Pb-Free.
http://onsemi.com
5
MC74HC4046A
SWITCHING WAVEFORMS
SIGIN, COMPIN INPUTS
VCC
50%
SIGIN INPUT
VCC
50%
GND VCC
50%
tPHL PCPOUT, PC1OUT PC3OUT OUTPUTS tTHL
90% 50% 10%
tPLH
GND
COMP IN INPUT PC2OUT tPZH
50%
tPHZ
90%
GND VOH HIGH IMPEDANCE
tTLH
OUTPUT
Figure 2.
Figure 3.
SIGIN INPUT
VCC
50%
TEST POINT GND OUTPUT DEVICE UNDER TEST C L*
COMPIN INPUT
VCC
50%
tPZL PC2OUT
OUTPUT 50%
tPLZ
GND HIGH IMPEDANCE
10%
VOL
*INCLUDES ALL PROBE AND JIG CAPACITANCE
Figure 4.
Figure 5. Test Circuit
http://onsemi.com
6
MC74HC4046A
DETAILED CIRCUIT DESCRIPTION
Voltage Controlled Oscillator/Demodulator Output
The VCO requires two or three external components to operate. These are R1, R2, C1. Resistor R1 and Capacitor C1 are selected to determine the center frequency of the VCO (see typical performance curves Figure 15). R2 can be used to set the offset frequency with 0 volts at VCO input. For example, if R2 is decreased, the offset frequency is increased. If R2 is omitted the VCO range is from 0 Hz. The effect of R2 is shown in Figure 25, typical performance curves. By increasing the value of R2 the lock range of the PLL is increased and the gain (volts/Hz) is decreased. Thus, for a narrow lock range, large swings on the VCO input will cause less frequency variation. Internally, the resistors set a current in a current mirror, as shown in Figure 6. The mirrored current drives one side of the capacitor. Once the voltage across the capacitor charges
VREF 12 R2 + _ I1
up to Vref of the comparators, the oscillator logic flips the capacitor which causes the mirror to charge the opposite side of the capacitor. The output from the internal logic is then taken to VCO output (Pin 4). The input to the VCO is a very high impedance CMOS input and thus will not load down the loop filter, easing the filters design. In order to make signals at the VCO input accessible without degrading the loop performance, the VCO input voltage is buffered through a unity gain Op-amp to Demod Output. This Op-amp can drive loads of 50K ohms or more and provides no loading effects to the VCO input voltage (see Figure 13). An inhibit input is provided to allow disabling of the VCO and all Op-amps (see Figure 6). This is useful if the internal VCO is not being used. A logic high on inhibit disables the VCO and all Op-amps, minimizing standby power consumption.
CURRENT MIRROR I1 + I2 = I3 9 11 R1 + _ I2 I3 4 VCOOUT
VCOIN
DEMOD OUT
10
+ _
C1 (EXTERNAL) 6 7
Vref + +
-
INH
5
Figure 6. Logic Diagram for VCO
The output of the VCO is a standard high speed CMOS output with an equivalent LS-TTL fan out of 10. The VCO output is approximately a square wave. This output can either directly feed the COMPIN of the phase comparators or
feed external prescalers (counters) to enable frequency synthesis.
http://onsemi.com
7
-
MC74HC4046A
Phase Comparators
All three phase comparators have two inputs, SIGIN and COMPIN. The SIGIN and COMPIN have a special DC bias network that enables AC coupling of input signals. If the signals are not AC coupled, standard 74HC input levels are required. Both input structures are shown in Figure 7. The
VCC SIGIN 14
outputs of these comparators are essentially standard 74HC outputs (comparator 2 is TRI-STATEABLE). In normal operation VCC and ground voltage levels are fed to the loop filter. This differs from some phase detectors which supply a current to the loop filter and should be considered in the design. (The MC14046 also provides a voltage).
VCC
PC2OUT 13
VCC COMPIN 3 PCPOUT 1 PC3OUT 15 PC1OUT 2
Figure 7. Logic Diagram for Phase Comparators Phase Comparator 1
This comparator is a simple XOR gate similar to the 74HC86. Its operation is similar to an overdriven balanced modulator. To maximize lock range the input frequencies must have a 50% duty cycle. Typical input and output waveforms are shown in Figure 8. The output of the phase detector feeds the loop filter which averages the output voltage. The frequency range upon which the PLL will lock onto if initially out of lock is defined as the capture range. The capture range for phase detector 1 is dependent on the loop filter design. The capture range can be as large as the lock range, which is equal to the VCO frequency range. To see how the detector operates, refer to Figure 8. When two square wave signals are applied to this comparator, an output waveform (whose duty cycle is dependent on the phase difference between the two signals) results. As the phase difference increases, the output duty cycle increases and the voltage after the loop filter increases. In order to achieve lock when the PLL input frequency increases, the VCO input voltage must increase and the phase difference between COMPIN and SIGIN will increase. At an input frequency equal to fmin, the VCO input is at 0 V. This requires the phase detector output to be grounded; hence, the
two input signals must be in phase. When the input frequency is fmax, the VCO input must be VCC and the phase detector inputs must be 180 degrees out of phase.
SIGIN COMP IN PC1OUT VCOIN VCC GND
Figure 8. Typical Waveforms for PLL Using Phase Comparator 1
The XOR is more susceptible to locking onto harmonics of the SIGIN than the digital phase detector 2. For instance, a signal 2 times the VCO frequency results in the same output duty cycle as a signal equal to the VCO frequency. The difference is that the output frequency of the 2f example is twice that of the other example. The loop filter and VCO range should be designed to prevent locking on to harmonics.
http://onsemi.com
8
MC74HC4046A
Phase Comparator 2
This detector is a digital memory network. It consists of four flip-flops and some gating logic, a three state output and a phase pulse output as shown in Figure 6. This comparator acts only on the positive edges of the input signals and is independent of duty cycle. Phase comparator 2 operates in such a way as to force the PLL into lock with 0 phase difference between the VCO output and the signal input positive waveform edges. Figure 8 shows some typical loop waveforms. First assume that SIGIN is leading the COMPIN. This means that the VCO's frequency must be increased to bring its leading edge into proper phase alignment. Thus the phase detector 2 output is set high. This will cause the loop filter to charge up the VCO input, increasing the VCO frequency. Once the leading edge of the COMPIN is detected, the output goes TRI-STATE holding the VCO input at the loop filter voltage. If the VCO still lags the SIGIN then the phase detector will again charge up the VCO input for the time between the leading edges of both waveforms. If the VCO leads the SIGIN then when the leading edge of the VCO is seen; the output of the phase comparator goes low. This discharges the loop filter until the leading edge of the SIGIN is detected at which time the output disables itself again. This has the effect of slowing down the VCO to again make the rising edges of both waveforms coincidental. When the PLL is out of lock, the VCO will be running either slower or faster than the SIGIN. If it is running slower the phase detector will see more SIGIN rising edges and so the output of the phase comparator will be high a majority of the time, raising the VCO's frequency. Conversely, if the VCO is running faster than the SIGIN, the output of the detector will be low most of the time and the VCO's output frequency will be decreased. As one can see, when the PLL is locked, the output of phase comparator 2 will be disabled except for minor corrections at the leading edge of the waveforms. When PC2 is TRI-STATED, the PCP output is high. This output can be used to determine when the PLL is in the locked condition. This detector has several interesting characteristics. Over the entire VCO frequency range there is no phase difference between the COMPIN and the SIGIN. The lock range of the PLL is the same as the capture range. Minimal power was consumed in the loop filter since in lock the detector output is a high impedance. When no SIGIN is present, the detector will see only VCO leading edges, so the comparator output will stay low, forcing the VCO to fmin. Phase comparator 2 is more susceptible to noise, causing the PLL to unlock. If a noise pulse is seen on the SIGIN, the comparator treats it as another positive edge of the SIGIN
and will cause the output to go high until the VCO leading edge is seen, potentially for an entire SIGIN period. This would cause the VCO to speed up during that time. When using PC1, the output of that phase detector would be disturbed for only the short duration of the noise spike and would cause less upset.
Phase Comparator 3
This is a positive edge-triggered sequential phase detector using an RS flip-flop as shown in Figure 7. When the PLL is using this comparator, the loop is controlled by positive signal transitions and the duty factors of SIG IN and COMP IN are not important. It has some similar characteristics to the edge sensitive comparator. To see how this detector works, assume input pulses are applied to the SIG IN and COMP IN 's as shown in Figure 10. When the SIGIN leads the COMPIN, the flop is set. This will charge the loop filter and cause the VCO to speed up, bringing the comparator into phase with the SIG IN. The phase angle between SIGIN and COMP IN varies from 0 to 360 and is 180 at fo. The voltage swing for PC3 is greater than for PC2 but consequently has more ripple in the signal to the VCO. When no SIG IN is present the VCO will be forced to fmax as opposed to fmin when PC2 is used. The operating characteristics of all three phase comparators should be compared to the requirements of the system design and the appropriate one should be used.
SIGIN COMP IN PC2OUT HIGH IMPEDANCE OFF-STATE VCOIN PCPOUT VCC GND
Figure 9. Typical Waveforms for PLL Using Phase Comparator 2
SIGIN COMP IN PC3OUT VCOIN VCC GND
Figure 10. Typical Waveform for PLL Using Phase Comparator 3
http://onsemi.com
9
MC74HC4046A
800 VCC=6.0 V 4.0 VCC=4.5 V VCC=3.0 V R I = (k ) 400 I I ( A)
VCC=3.0 V
VCC=4.5 V VCC=6.0 V
0
0 1/2 VCC-1.0 V
1/2 VCC VI (V)
1/2 VCC+1.0 V
-4.0 1/2VCC - 500 mV
1/2 VCC VI (V)
1/2 VCC + 500 mV
Figure 11. Input Resistance at SIGIN, COMPIN with DVI = 1.0 V at Self-Bias Point
DEMOD OUT 6.0
Figure 12. Input Current at SIGIN, COMPIN with DVI = 500 mV at Self-Bias Point
15 10 5.0 0 R1=100 kW R1=300 kW VCC = 3.0 V C1 = 100 pF; R2 = ; VVCOIN=1/3 VCC 0 50 100 AMBIENT TEMPERATURE (C) 150 R1=3.0 kW R1=100 kW R1=300 kW
VDEM OUT
VCC=6.0 V RS=300 k VCC=6.0 V RS=50 k VCC=4.5 V RS=300 k VCC=4.5 V RS=50 k VCC=3.0 V RS=300 k VCC=3.0 V RS=50 k
0 0
FREQUENCY STABILITY (%)
-5.0 -10
R1=3.0 kW 6.0 -15 -100 -50
3.0 VCOIN (V)
Figure 13. Offset Voltage at Demodulator Output as a Function of VCOIN and RS
R1=3.0 kW FREQUENCY STABILITY (%) R1=300 kW R1=100 kW
Figure 13A. Frequency Stability versus Ambient Temperature: VCC = 3.0 V
15 FREQUENCY STABILITY (%) 10 5.0 0 -5.0 -10 -15 -100 -50
10 8.0 6.0 4.0 2.0 0 -2.0 -4.0 -6.0 -8.0 -10 -100
R1=3.0 kW R1=300 kW R1=100 kW
VCC = 4.5 V C1 = 100 pF; R2 = ; VVCOIN = 1/2 V CC 0 50 100 AMBIENT TEMPERATURE (C) 150
VCC = 6.0 V C1 = 100 pF; R2 = ; VVCOIN=1/2 VCC -50 0 50 100 150 AMBIENT TEMPERATURE (C)
Figure 13B. Frequency Stability versus Ambient Temperature: VCC = 4.5 V
Figure 13C. Frequency Stability versus Ambient Temperature: VCC = 6.0 V
http://onsemi.com
10
MC74HC4046A
23 21 19 50 70
VCC = 6.0 V
60
VCC = 4.5 V VCC = 3.0 V
VCC = 6.0 V
f VCO(MHz)
f VCO (KHz)
17 15 13 11 9 7.0 0 0.5 1.0 1.5 2.0 2.5
VCC = 4.5 V
40 30 20
VCC = 3.0 V
R1 = 3.0 kW C1 = 39 pF 3.0 3.5 4.0
10 0
R1 = 3.0 kW C1 = 0.1 mF 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0
VVCOIN (V)
VVCOIN (V)
Figure 14A. VCO Frequency (fVCO) as a Function of the VCO Input Voltage (VVCOIN)
2.0 1.0
Figure 14B. VCO Frequency (fVCO) as a Function of the VCO Input Voltage (VVCOIN)
VCC = 4.5 V VCC = 6.0 V VCC = 3.0 V f VCO(MHz) f VCO (KHz)
1.0
0.9 0.8 0.7 0.6 0.5 0.4 0.3 R1 = 300 kW C1 = 39 pF 0.2 0.1 4.5 0 0 0.5 1.0 1.5 2.0 2.5 3.0
VCC = 6.0 V VCC = 4.5 V VCC = 3.0 V
R1 = 300 kW C1 = 0.1 mF 3.5 4.0 4.5
0
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
VVCOIN (V)
VVCOIN (V)
Figure 14C. VCO Frequency (fVCO) as a Function of the VCO Input Voltage (VVCOIN)
2.0
Figure 14D. VCO Frequency (fVCO) as a Function of the VCO Input Voltage (VVCOIN)
VCC= 4.5 V 6.0 V 3.0 V
C1 = 1.0 mF
1.0
f2 f0 f0 f1
f VCO (%)
0
4.5 V
-1.0
6.0 V
C1 = 39 pF R2 = ; DV = 0.5 V
-2.0
3.0 V
10 0
101
R1 (kW)
102
103
MIN
1/2 VCC
MAX
DV = 0.5 V OVER THE VCC RANGE: FOR VCO LINEARITY f0 = (f1 + f2) / 2 LINEARITY = (f0 - f0) / f0) x 100%
Figure 15A. Frequency Linearity versus R1, C1 and VCC
Figure 15B. Definition of VCO Frequency Linearity
http://onsemi.com
11
MC74HC4046A
106
CL = 50 pF; R2 = ; VVCOIN = 1/2 VCC FOR VCC = 4.5 V AND 6.0 V; VVCOIN = 1/3 VCC FOR VCC = 3.0 V; Tamb = 25C
106
CL = 50 pF; R1 = ; VVCOIN = 0 V; Tamb = 25C
PR1 ( W)
VCC = 6.0 V, C1 = 40 pF VCC = 6.0 V, C1 = 1.0 mF
PR2 ( W)
105
105
VCC = 6.0 V, C1 = 40 pF VCC = 6.0 V, C1 = 1.0 mF VCC = 4.5 V, C1 = 40 pF VCC = 4.5 V, C1 = 1.0 mF
104
VCC = 4.5 V, C1 = 40 pF VCC = 4.5 V, C1 = 1.0 mF VCC = 3.0 V, C1 = 40 pF
104
103
VCC = 3.0 V, C1 = 1.0 mF
100
101
R1 (kW)
102
103
103
VCC = 3.0 V, C1 = 1.0 mF
VCC = 3.0 V, C1 = 40 pF
100
101
R2 (kW)
102
103
Figure 16. Power Dissipation versus R1
Figure 17. Power Dissipation versus R2
103
108
R1 = R2 = ; Tamb = 25C
107 106 (Hz)
VCC=6.0 V VCC=4.5 V
PDEM ( W)
102
VCO
105 104 103 102
VCC = 6.0 V 4.5 V 3.0 V 6.0 V 4.5 V 3.0 V 6.0 V 4.5 V 3.0 V
INH = GND; Tamb = 25C; R2 = ; VVCOIN = 1/3 VCC
R1=3.0 kW
101
f
VCC=3.0 V
R1=100 kW R1=300 kW
100 101 102 RS (kW) 103
101
102
103 C1 (pF)
104
105
106
Figure 18. DC Power Dissipation of Demodulator versus RS
Figure 19. VCO Center Frequency versus C1
108 107 106 off (Hz) 105 104 103 102 101
VCC = 6.0 V 4.5 V 3.0 V 6.0 V 4.5 V 3.0 V 6.0 V 4.5 V 3.0 V
R1 = ; VVCOIN = 1/2 VCC FOR VCC = 4.5 V AND 6.0 V; VVCOIN = 1/3 VCC FOR VCC = 3.0 V; INH = GND; Tamb = 25C
108 107 106 105 104 VCC = 4.5 V; R2 =
f
R2=3.0 kW
R2=100 kW R2=300 kW
2fL (Hz) 102 103 C1 (pF) 104 105 106
103 102
101
10-7
10-6
10-5
10-4 R1C1
10-3
10-2
10-1
Figure 20. Frequency Offset versus C1
Figure 21. Typical Frequency Lock Range (2fL) versus R1C1
http://onsemi.com
12
MC74HC4046A
20
R1=3.0 kW R1=10 kW R1=20 kW R1=30 kW
14 12 10 FREQ. (MHz) 8.0 6.0 4.0 2.0 0 104 105 -2.0 100 101 102 103 R2 ( kW) 104
R1=3 kW R1=10 kW R1=20 kW R1=30 kW R1=40 kW R1=50 kW R1=100 kW R1=300 kW
C1=39 pF
15 FREQ. (MHz)
10
R1=40 kW R1=50 kW
5.0
R1=100 kW
0 1.0
C1=39 pF 101 102 R2 ( kW)
R1=300 kW
103
105
106
Figure 22. R2 versus fmax
20 C1=39 pF
Figure 23. R2 versus fmin
2f L (MHz)
R1=10 kW R1=3.0 kW R1=20 kW
10
R1=30 kW R1=40 kW R1=50 kW R1=100 kW R1=300 kW
0
1.0
101
102
R2 ( kW)
103
104
105
Figure 24. R2 versus Frequency Lock Range (2fL)
http://onsemi.com
13
MC74HC4046A
APPLICATION INFORMATION The following information is a guide for approximate values of R1, R2, and C1. Figures 20, 21, and 22 should be used as references as indicated below, also the values of R1, R2, and C1 should not violate the Maximum values indicated in the DC ELECTRICAL CHARACTERISTICS tables.
Phase Comparator 1 R2 = * Given f0 * Use f0 with Figure 19 to determine R1 and C1. (see Figure 24 for characteristics of the VCO operation) R2 0 R * Given f0 and fL * Calculate fmin fmin = f0-fL * Determine values of C1 and R2 from Figure 21. * Determine R1-C1 from Figure 22. * Calculate value of R1 from the value of C1 and the product of R1C1 from Figure 22. (see Figure 25 for characteristics of the VCO operation) Phase Comparator 2 R2 = * Given fmax and f0 * Determine the value of R1 and C1 using Figure 20 and use Figure 22 to obtain 2fL and then use this to calculate fmin. R2 0 R * Given f0 and fL * Calculate fmin fmin = f0-fL * Determine values of C1 and R2 from Figure 21. * Determine R1-C1 from Figure 22. * Calculate value of R1 from the value of C1 and the product of R1C1 from Figure 22. (see Figure 25 for characteristics of the VCO operation) Phase Comparator 3 R2 = * Given fmax and f0 * Determine the value of R1 and C1 using Figure 20 and Figure 22 to obtain 2fL and then use this to calculate fmin. R2 0 R * Given f0 and fL * Calculate fmin: fmin = f0-fL * Determine values of C1 and R2 from Figure 21. * Determine R1-C1 from Figure 22. * Calculate value of R1 from the value of C1 and the product of R1C1 from Figure 22. (see Figure 25 for characteristics of the VCO operation)
http://onsemi.com
14
MC74HC4046A
PACKAGE DIMENSIONS
PDIP-16 N SUFFIX CASE 648-08 ISSUE T
-A-
16 9
B
1 8
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL. 4. DIMENSION B DOES NOT INCLUDE MOLD FLASH. 5. ROUNDED CORNERS OPTIONAL.
F S
C
L
-T- H G D
16 PL
SEATING PLANE
K
J TA
M
M
0.25 (0.010)
M
DIM A B C D F G H J K L M S
INCHES MIN MAX 0.740 0.770 0.250 0.270 0.145 0.175 0.015 0.021 0.040 0.70 0.100 BSC 0.050 BSC 0.008 0.015 0.110 0.130 0.295 0.305 0_ 10 _ 0.020 0.040
MILLIMETERS MIN MAX 18.80 19.55 6.35 6.85 3.69 4.44 0.39 0.53 1.02 1.77 2.54 BSC 1.27 BSC 0.21 0.38 2.80 3.30 7.50 7.74 0_ 10 _ 0.51 1.01
SOIC-16 D SUFFIX CASE 751B-05 ISSUE J
-A-
16 9 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. DIM A B C D F G J K M P R MILLIMETERS MIN MAX 9.80 10.00 3.80 4.00 1.35 1.75 0.35 0.49 0.40 1.25 1.27 BSC 0.19 0.25 0.10 0.25 0_ 7_ 5.80 6.20 0.25 0.50 INCHES MIN MAX 0.386 0.393 0.150 0.157 0.054 0.068 0.014 0.019 0.016 0.049 0.050 BSC 0.008 0.009 0.004 0.009 0_ 7_ 0.229 0.244 0.010 0.019
-B-
1 8
P
8 PL
0.25 (0.010)
M
B
S
G F
K C -T-
SEATING PLANE
R
X 45 _
M D
16 PL M
J
0.25 (0.010)
TB
S
A
S
http://onsemi.com
15
MC74HC4046A
PACKAGE DIMENSIONS
TSSOP-16 DT SUFFIX CASE 948F-01 ISSUE A
16X K REF
0.10 (0.004) 0.15 (0.006) T U
S
M
TU
S
V
S
K
16
2X
L/2
9
J1 B -U-
L
PIN 1 IDENT. 1 8
J
N 0.15 (0.006) T U
S
0.25 (0.010) M
A -V- N F DETAIL E
C 0.10 (0.004) -T- SEATING
PLANE
H D G
DETAIL E
http://onsemi.com
16
CCC EEE CCC EEE CCC
K1
SECTION N-N
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A DOES NOT INCLUDE MOLD FLASH. PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.010) PER SIDE. 5. DIMENSION K DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE K DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 7. DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE -W-. MILLIMETERS MIN MAX 4.90 5.10 4.30 4.50 --- 1.20 0.05 0.15 0.50 0.75 0.65 BSC 0.18 0.28 0.09 0.20 0.09 0.16 0.19 0.30 0.19 0.25 6.40 BSC 0_ 8_ INCHES MIN MAX 0.193 0.200 0.169 0.177 --- 0.047 0.002 0.006 0.020 0.030 0.026 BSC 0.007 0.011 0.004 0.008 0.004 0.006 0.007 0.012 0.007 0.010 0.252 BSC 0_ 8_
-W-
DIM A B C D F G H J J1 K K1 L M
MC74HC4046A
PACKAGE DIMENSIONS
SOEIAJ-16 F SUFFIX CASE 966-01 ISSUE O
16
9
LE Q1 E HE M_ L DETAIL P
1
8
Z D e A VIEW P
c
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS D AND E DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS AND ARE MEASURED AT THE PARTING LINE. MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 5. THE LEAD WIDTH DIMENSION (b) DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE LEAD WIDTH DIMENSION AT MAXIMUM MATERIAL CONDITION. DAMBAR CANNOT BE LOCATED ON THE LOWER RADIUS OR THE FOOT. MINIMUM SPACE BETWEEN PROTRUSIONS AND ADJACENT LEAD TO BE 0.46 ( 0.018). DIM A A1 b c D E e HE L LE M Q1 Z MILLIMETERS MIN MAX --- 2.05 0.05 0.20 0.35 0.50 0.18 0.27 9.90 10.50 5.10 5.45 1.27 BSC 7.40 8.20 0.50 0.85 1.10 1.50 10 _ 0_ 0.70 0.90 --- 0.78 INCHES MIN MAX --- 0.081 0.002 0.008 0.014 0.020 0.007 0.011 0.390 0.413 0.201 0.215 0.050 BSC 0.291 0.323 0.020 0.033 0.043 0.059 10 _ 0_ 0.028 0.035 --- 0.031
b 0.13 (0.005)
M
A1 0.10 (0.004)
http://onsemi.com
17
MC74HC4046A
ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. "Typical" parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
LITERATURE FULFILLMENT: N. American Technical Support: 800-282-9855 Toll Free Literature Distribution Center for ON Semiconductor USA/Canada P.O. Box 61312, Phoenix, Arizona 85082-1312 USA Phone: 480-829-7710 or 800-344-3860 Toll Free USA/Canada Japan: ON Semiconductor, Japan Customer Focus Center 2-9-1 Kamimeguro, Meguro-ku, Tokyo, Japan 153-0051 Fax: 480-829-7709 or 800-344-3867 Toll Free USA/Canada Phone: 81-3-5773-3850 Email: orderlit@onsemi.com ON Semiconductor Website: http://onsemi.com Order Literature: http://www.onsemi.com/litorder For additional information, please contact your local Sales Representative.
http://onsemi.com
18
MC74HC4046A/D

▲Up To Search▲

Price & Availability of MC74HC4046ADG

	To Download MC74HC4046ADG Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .